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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16772A
480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The PD16772A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 - 0.1 V, level inversion operation of the LCD's common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels.
FEATURES
* CMOS level input (2.3 to 3.6 V) * 480 outputs * Input of 6 bits (gradation data) by 6 dots * Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC) * Output dynamic range : VSS2 + 0.1 V to VDD2 - 0.1 V * High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) * Apply for dot-line inversion, n-line inversion and column line inversion * Output voltage polarity inversion function (POL) * Display data inversion function (POL21/22) * Current consumption reduction function (LPC, Bcont) * Logic power supply voltage (VDD1) : 2.3 to 3.6 V * Driver power supply voltage (VDD2) : 8.5 V 0.5 V
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16772AN-xxx
Remark
The TCP's external shape is customized. To order the required shape, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14725EJ1V0DS00 (1st edition) Date Published August 2000 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
2000
PD16772A
1. BLOCK DIAGRAM
STHR R,/L CLK STB C1 C2 STHL VDD1 VSS1 C79 C80
80-bit bidirectional shift register
D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL21/22
Data register
POL
Latch
VDD2 Level shifter VSS2
V0 - V9
D/A converter
LPC Bcont
Voltage follower output
S1
S2
S3
S480
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1 S2 S479 S480
V0 V4 V5 V9 Multiplexer
5
6-bit D/A converter 5
POL
2
Data Sheet S14725EJ1V0DS00
PD16772A
3. PIN CONFIGURATION (PD16772AN-xxx: TCP (TAB package))
STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR
S480 S479 S478 S477
Copper Foil Surface
S4 S3 S2 S1
Remark
This figure does not specify the TCP package.
Data Sheet S14725EJ1V0DS00
3
PD16772A
4. PIN FUNCTIONS
Pin Symbol S1 to S480 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift input directions of the shift registers are as follows. R,/L = H: STHR input, S1 S480, STHL output R,/L = L: STHL input, S480 S1, STHR output Right shift start pulse These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. input/output Left shift start pulse R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output input/output The start pulse width (H level) for next-level drivers is 1CLK. Shift clock input Refers to the shift register's shift clock input. The display data is incorporated into the data th register at the rising edge. At the rising edge of the 80 clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB's rising edge. The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL = L: The S2n-1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n-1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time(tPOL-STB) with respect to STB's rising edge. Data inversion can invert when display data is loaded. POL21/22 = H : Data inversion loads display data after inverting it. POL21/22 = L : Data inversion does not invert input data. POL21: D00 to D05, D10 to D15, D20 to D25 POL22: D30 to D35, D40 to D45, D50 to D55 The current consumption of VDD2 is lowered by controlling the constant current source of the output amplifier. This pin is pulled up to the VDD1 power supply inside the IC. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. This pin can be used to finely control the bias current inside the output amplifier. When this fine-control function is not required, leave this pin open. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. Input the -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 - 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V 2.3 to 3.6 V 8.5 V 0.5 V Grounding Grounding Pin Name Driver output Display data input Description The D/A converted 64-gray-scale analog voltage is output. The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB
STHR STHL
CLK
STB
Latch input
POL
Polarity input
POL21, POL22
Data inversion input
LPC
Low power control input Bias control
Bcont
V0 to V9
-corrected power supplies
VDD1 VDD2 VSS1 VSS2
Logic power supply Driver power supply Logic ground Driver ground
4
Data Sheet S14725EJ1V0DS00
PD16772A
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is possible.). 2. To stabilize the supply voltage, please be sure to insert a 0.1 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the -corrected power supply terminals (V0, V1, V2,....., V9) and VSS2.
Data Sheet S14725EJ1V0DS00
5
PD16772A
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The PD16772A incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel -compensated voltages to V0' to V63' and V0" to V63" is almost equivalent. For the 2 sets of five -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies V1 to V3 and V6 to V8. Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 - 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V Figures 5-2 and 5-3 show the relationship between the input data and the output voltage and the resistance values of the resistor strings. Figure 5-1. Relationship between Input Data and -corrected Power Supplies
VDD2 0.1 V V0
16
V1 16 V2 V3 15 V4 VCOM V5 15 V6 V7 V8 16 16 Split interval 16
16
V9 0.1 V VSS2 00 10 20 Input data (HEX) 30 3F
6
Data Sheet S14725EJ1V0DS00
PD16772A
Figure 5-2. Relationship between Input Data and Output Voltage VDD2 - 0.2 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2, POL21/22 = L
V0 r0 V1' r1 V2' r2 V3' r3 V0'
Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17 V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output votage V0 V1+(V0-V1)x 6500 V1+(V0-V1)x 5800 V1+(V0-V1)x 5100 V1+(V0-V1)x 4400 V1+(V0-V1)x 3700 V1+(V0-V1)x 3350 V1+(V0-V1)x 3000 V1+(V0-V1)x 2650 V1+(V0-V1)x 2300 V1+(V0-V1)x 1950 V1+(V0-V1)x 1600 V1+(V0-V1)x 1250 V1+(V0-V1)x 900 V1+(V0-V1)x 600 V1+(V0-V1)x 300 V1 V2+(V1-V2)x 2100 V2+(V1-V2)x 1900 V2+(V1-V2)x 1700 V2+(V1-V2)x 1500 V2+(V1-V2)x 1300 V2+(V1-V2)x 1150 V2+(V1-V2)x 1000 V2+(V1-V2)x 850 V2+(V1-V2)x 700 V2+(V1-V2)x 600 V2+(V1-V2)x 500 V2+(V1-V2)x 400 V2+(V1-V2)x 300 V2+(V1-V2)x 200 V2+(V1-V2)x 100 V2 V3+(V2-V3)x 1550 V3+(V2-V3)x 1450 V3+(V2-V3)x 1350 V3+(V2-V3)x 1250 V3+(V2-V3)x 1150 V3+(V2-V3)x 1050 V3+(V2-V3)x 950 V3+(V2-V3)x 850 V3+(V2-V3)x 750 V3+(V2-V3)x 650 V3+(V2-V3)x 550 V3+(V2-V3)x 450 V3+(V2-V3)x 350 V3+(V2-V3)x 250 V3+(V2-V3)x 150 V3 V4+(V3-V4)x 4100 V4+(V3-V4)x 3950 V4+(V3-V4)x 3800 V4+(V3-V4)x 3650 V4+(V3-V4)x 3500 V4+(V3-V4)x 3350 V4+(V3-V4)x 3200 V4+(V3-V4)x 2950 V4+(V3-V4)x 2700 V4+(V3-V4)x 2450 V4+(V3-V4)x 2150 V4+(V3-V4)x 1850 V4+(V3-V4)x 1550 V4+(V3-V4)x 1100 V4 rn r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 r total () 1150 700 700 700 700 350 350 350 350 350 350 350 350 300 300 300 200 200 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 150 150 150 150 150 250 250 250 300 300 300 450 1100 15850
r14 V15' r15 V1 r16 V17' r17 V16'
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250
r46 r47 V3 r48 V49' r49 V47' V48'
r60 r61 r62 V4 V63' V61' V62'
Caution
There is no connection between V4 and V5 terminal in the chip.
Data Sheet S14725EJ1V0DS00
7
PD16772A
Figure 5-3. Relationship between Input Data and Output Voltage 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V, POL21/22 = L
V5 V63'' r62 V62'' r61 V61'' r60 V60'' r59
Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0" V1" V2" V3" V4" V5" V6" V7" V8" V9" V10" V11" V12" V13" V14" V15" V16" V17" V18" V19" V20" V21" V22" V23" V24" V25" V26" V27" V28" V29" V30" V31" V32" V33" V34" V35" V36" V37" V38" V39" V40" V41" V42" V43" V44" V45" V46" V47" V48" V49" V50" V51" V52" V53" V54" V55" V56" V57" V58" V59" V60" V61" V62" V63" Output voltage V9 V9+(V8-V9)x 1150 V9+(V8-V9)x 1850 V9+(V8-V9)x 2550 V9+(V8-V9)x 3250 V9+(V8-V9)x 3950 V9+(V8-V9)x 4300 V9+(V8-V9)x 4650 V9+(V8-V9)x 5000 V9+(V8-V9)x 5350 V9+(V8-V9)x 5700 V9+(V8-V9)x 6050 V9+(V8-V9)x 6400 V9+(V8-V9)x 6750 V9+(V8-V9)x 7050 V9+(V8-V9)x 7350 V8 V8+(V7-V8)x 200 V8+(V7-V8)x 400 V8+(V7-V8)x 600 V8+(V7-V8)x 800 V8+(V7-V8)x 1000 V8+(V7-V8)x 1150 V8+(V7-V8)x 1300 V8+(V7-V8)x 1450 V8+(V7-V8)x 1600 V8+(V7-V8)x 1700 V8+(V7-V8)x 1800 V8+(V7-V8)x 1900 V8+(V7-V8)x 2000 V8+(V7-V8)x 2100 V8+(V7-V8)x 2200 V7 V7+(V6-V7)x 100 V7+(V6-V7)x 200 V7+(V6-V7)x 300 V7+(V6-V7)x 400 V7+(V6-V7)x 500 V7+(V6-V7)x 600 V7+(V6-V7)x 700 V7+(V6-V7)x 800 V7+(V6-V7)x 900 V7+(V6-V7)x 1000 V7+(V6-V7)x 1100 V7+(V6-V7)x 1200 V7+(V6-V7)x 1300 V7+(V6-V7)x 1400 V7+(V6-V7)x 1500 V6 V6+(V5-V6)x 150 V6+(V5-V6)x 300 V6+(V5-V6)x 450 V6+(V5-V6)x 600 V6+(V5-V6)x 750 V6+(V5-V6)x 900 V6+(V5-V6)x 1050 V6+(V5-V6)x 1300 V6+(V5-V6)x 1550 V6+(V5-V6)x 1800 V6+(V5-V6)x 2100 V6+(V5-V6)x 2400 V6+(V5-V6)x 2700 V6+(V5-V6)x 3150 V5 rn r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 r total () 1150 700 700 700 700 350 350 350 350 350 350 350 350 300 300 300 200 200 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 150 150 150 150 150 250 250 250 300 300 300 450 1100 15850
r49 V49'' r48 V6 r47 V47'' r46 V48''
/ / / / / / / / / / / / / /
7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250
/ / / / / / / / / / / / / /
r17 V17'' r16 V8 r15 V15'' r14 V16''
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / /
r2 V2'' r1 V1'' r0 V9 V0''
Caution
There is no connection between V4 and V5 terminal in the chip.
8
Data Sheet S14725EJ1V0DS00
PD16772A
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 xxx xxx S479 D40 to D45 S480 D50 to D55
(2) R,/L = L (Left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 xxx xxx S479 D40 to D45 S480 D50 to D55
POL L H
S2n-1
Note
S2n
Note
V0 to V4 V5 to V9
V5 to V9 V0 to V4
Note S2n-1 (Odd output), S2n (Even output)
7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n-1
Selected voltage V0 to V4
Selected voltage V5 to V9
Selected voltage V0 to V4
S2n
Selected voltage V5 to V9
Selected voltage V0 to V4
Selected voltage V5 to V9
Hi-Z
Hi-Z
Hi-Z
Data Sheet S14725EJ1V0DS00
9
PD16772A
8. RELATIONSHIP BETWEEN STB, CLK AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure 8-1. Output Circuit Block Diagram
Output Amp
DAC
+
VAMP(IN) SW1 Sn (VOUT)
Figure 8-2. Output Circuit Timing Waveform
[1]
CLK (External Input) STB (External Input) SW1 : ON
[2]
SW1 : OFF
SW1 : ON
VAMP(IN)
Sn (VOUT: External output) Output Hi-Z Output
Remarks 1. STB = L : SW1 = ON STB = H : SW1 = OFF 2. STB = "H" is acknowledged at timing [1]. 3. The display data latch is compensated at timing [2] and the input voltage (VAMP(IN) : grayscale level voltage) of the output amplifier changes.
10
Data Sheet S14725EJ1V0DS00
PD16772A
9. CURRENT CONSUMPTION REDUCTION FUNCTION
The PD16772A has a low power control function (LPC) which can switch the bias current of the output amplifier between two levels and a bias control function (Bcont) which can be used to finely control the bias current. * Low Power Control Function (LPC) The bias current of the output amplifier can be switched between two levels using this pin (Bcont: Open). LPC = H or Open: Low power mode LPC = L: Normal power mode The VDD2 of static current consumption can be reduced to two thirds of that in normal mode. Input a stable DC current (VDD1/VSS1) to this pin. * Bias Current Control Function (Bcont) It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9-1. Bias Current Control Function (Bcont)
PD16772A
Bcont LPC
REXT
H/L
VSS2
Refer to the table below for the percentage of current regulation when using the bias current control function. Table 9-1. Current Consumption Regulation Percentage Compared to Normal Mode
REXT
Current Consumption Regulation Percentage LPC = L LPC = H/Open 65% 80% 100% 210% VDD1 = 3.3 V VDD2 = 8.7 V
(Open) 50 k 20 k 0
100% 120% 140% 240%
Remark The above current consumption regulation percentages are not product-characteristic guaranteed as they re based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
Data Sheet S14725EJ1V0DS00
11
PD16772A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Logic Part Input Voltage Driver Part Input Voltage Logic Part Output Voltage Driver Part Output Voltage Operating Ambient Temperature Storage Temperature VDD1 VDD2 VI1 VI2 VO1 VO2 TA Tstg Symbol Rating -0.5 to +4.0 -0.5 to +10.0 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -10 to +75 -55 to +125 Unit V V V V V V C C
5 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = -10 to +75C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage High-Level Input Voltage Low-Level Input Voltage VDD1 VDD2 VIH VIL V0 to V9 VO fCLK VDD2 = 2.3 V Symbol Condition MIN. 2.3 8.0 0.7 VDD1 0 VSS2 + 0.1 VSS2 + 0.1 8.5 TYP. MAX. 3.6 9.0 VDD1 0.3 VDD1 VDD2 - 0.1 VDD2 - 0.1 45 Unit V V V V V V MHz
-Corrected Voltage
Driver Part Output Voltage Clock Frequency
12
Data Sheet S14725EJ1V0DS00
PD16772A
Electrical Characteristics (TA = -10 to +75C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, the input level is defined to be LPC = L, Bcont = Open)
Parameter Input Leak Current High-Level Output Voltage Low-Level Output Voltage Symbol IIL VOH VOL I STHR (STHL), IOH = 0 mA STHR (STHL), IOL = 0 mA VDD2 = 8.5 V V0 pin, V5 pin 126 -504 252 -252 VDD1 - 0.1 0.1 504 -126 Condition MIN. TYP. MAX. 1.0 Unit
A
V V
-Corrected Supply Current
A A A A
V0 to V4 = V5 to V9 = V4 pin, V9 pin 4.0 V Driver Output Current IVOH IVOL Output Voltage Deviation Output Swing Difference Deviation VO VP-P VX = 7.0 V, VOUT = 6.5 V
Note Note
-30 30 7 2 20 15
VX = 1.0 V, VOUT = 1.5 V TA = 25C
mV mV
VDD1 = 3.3 V, VDD2 = 8.5 V VOUT = 2.0 V, 4.25 V, 6.5 V
5 5
Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption
IDD1
VDD1
1.0
7.5
mA
IDD2
VDD2, with no load
3.5
7.5
mA
Note VX refers to the output voltage of analog output pins S1 to S480. VOUT refers to the voltage applied to analog output pins S1 to S480. 5 Cautions 1. fSTB = 50 kHz, fCLK = 40 MHz. 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of UXGA single-sided mounting (10 units). Switching Characteristics (TA = -10 to +75C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, the input level is defined to be LPC = L, Bcont = Open)
Parameter Start Pulse Delay Time Symbol tPLH1 tPHL1 CL = 10 pF Condition MIN. TYP. 10 10 CL = 75 pF, RL = 5 k 2.5 5 2.5 5 STHR (STHL) excluded, TA = 25C STHR (STHL),TA = 25C 5 8 MAX. 20 20 5 8 5 8 10 10 Unit ns ns
5 5 5 5
Driver Output Delay Time
tPLH2 tPLH3 tPHL2 tPHL3
s s s s
pF pF
Input Capacitance
CI1 CI2
Data Sheet S14725EJ1V0DS00
13
PD16772A
5 Timing Requirements (TA = -10 to +75C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter Clock Pulse Width Clock Pulse High Period Clock Pulse Low Period Symbol PWCLK PWCLK(H) PWCLK(L) VDD1 = 2.3 to 3.0 V VDD1 = 3.0 to 3.6 V Data Setup Time Data Hold Time Start Pulse Setup Time Start Pulse Hold Time POL21/22 Setup Time POL21/22 Hold Time tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP3 tHOLD3 VDD1 = 2.3 to 3.0 V VDD1 = 3.0 to 3.6 V Start Pulse Low Period STB Pulse Width Last Data Timing CLK-STB Time STB-CLK Time tSPL PWSTB tLDT tCLK-STB tSTB-CLK CLK STB STB CLK VDD1 = 2.3 to 3.0 V STB CLK VDD1 = 3.0 to 3.6 V Time Between STB and Start Pulse POL-STB Time STB-POL Time tSTB-STH tPOL-STB tSTB-POL STB STHR(STHL) POL or STB STB POL or 2 -5 6 CLK ns ns 6 ns Condition VDD1 = 2.3 to 3.6 V MIN. 22 4 7 4 3 0 3 0 3 1 0 1 2 2 6 14 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK ns ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
14
Data Sheet S14725EJ1V0DS00
11. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK(L) PWCLK CLK tSETUP2 STHR (1st Dr.) tSETUP1 Dn0 to Dn5 INVALID D1 to D6 1 tHOLD2 2
PWCLK(H) 3 80 81 82 801 802 tCLK-STB tSTB-CLK tSPL
1
2 90%
tr
tf VDD1
10%
VSS1 VDD1 VSS1
tHOLD1 D469 to D474 D475 to D480 D481 to D486 D4795 to D4800
tSTB-STH VDD1 INVALID D1-D6 D7-D12 VSS1
D7 to D12 tHOLD3
tSETUP3 POL21/22 INVALID
VDD1 INVALID VSS1 tPLH1 STHL (1st Dr.) tLDT STB VSS1 tPOL-STB POL VSS1 tPLH3 Hi-Z tPLH2 tSTB-POL VDD1 PWSTB VDD1 tPHL1 VDD1 VSS1
Data Sheet S14725EJ1V0DS00
Sn (VOUT)
Target Voltage 0.1 VDD2 6-bit accuracy
PD16772A
tPHL2 tPHL3
15
PD16772A
12. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16772A. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16772AN-xxx: TCP (TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C, heating for 2 to 3 seconds : pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C : pressure 3 to 8 kg/cm : time 3 to 5 sec. Real bonding 165 to 180C: pressure 25 to 45 kg/cm : time 30 to 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
2 2
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
16
Data Sheet S14725EJ1V0DS00
PD16772A
[MEMO]
Data Sheet S14725EJ1V0DS00
17
PD16772A
[MEMO]
18
Data Sheet S14725EJ1V0DS00
PD16772A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14725EJ1V0DS00
19

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